DEIXE SEU LIKE!

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

SEU Emulation Environment

www.xilinx.com 1 © Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Testing for the effects of soft errors can be challenging, frustrating, and expensive. The options are fe...

متن کامل

Rosetta SEU Study

Results were previously presented [2] from real-time experiments that evaluated large FPGAs fabricated in different CMOS technologies (0.15μ, 0.13μ and 90 nanometer) for their sensitivity to radiationinduced single-event upsets. These results were compared to circuit simulation (Qcrit) studies, as well as to LANSCE neutron beam results and Crocker Nuclear Laboratory (U. C. Davis) cyclotron prot...

متن کامل

SEU-Tolerant QDI Circuits

This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a general method to make QDI circuits SEU-tolerant. We present a simplified SEUtolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comp...

متن کامل

SEU-Resistant Magnetic Flip Flops

The development of a practical magnetic tunneling junction (MTJ) ten years ago allowed the creation of a new class of non-volatile memories. This technology may offer superior resistance to total ionizing dose and virtually unlimited write endurance, making it more attractive than flash memories for space applications. Although a number of manufacturers are developing high-density bulk magnetic...

متن کامل

Low Power Dissipation SEU-hardened CMOS Latch

This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is show...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Revista Brasileira de Pesquisa em Turismo

سال: 2020

ISSN: 1982-6125

DOI: 10.7784/rbtur.v14i3.1889